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<!@TC:1704441242>
# Fri Jan  5 15:54:01 2024


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: D:\lscc\diamond\3.12\synpbase
OS: Windows 6.2

Hostname: WOO

Implementation : impl1
<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 119MB)


Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 131MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1704441242> | No constraint file specified. 
4.0\lab8_prox_detect\impl1\prox_detect_impl1_scck.rpt <a href="E:\fpgaproject\stepbaseboard\STEP-MXO2:@XP_FILE">STEP-MXO2</a>
See clock summary report "E:\fpgaproject\stepbaseboard\STEP-MXO2 4.0\lab8_prox_detect\impl1\prox_detect_impl1_scck.rpt"
@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1704441242> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1704441242> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1704441242> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 131MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 131MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 141MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)

@N:<a href="@N:FX493:@XP_HELP">FX493</a> : <!@TM:1704441242> | Applying initial value "0" on instance clk_40khz. 
<font color=#A52A2A>@W:<a href="@W:FX474:@XP_HELP">FX474</a> : <!@TM:1704441242> | User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. </font> 
Encoding state machine state[8:0] (in view: work.rpr0521rs_driver(verilog))
original code -> new code
   0000 -> 000000001
   0001 -> 000000010
   0010 -> 000000100
   0011 -> 000001000
   0100 -> 000010000
   0101 -> 000100000
   0110 -> 001000000
   0111 -> 010000000
   1000 -> 100000000
Encoding state machine state[2:0] (in view: work.segment_scan(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10

Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 176MB peak: 176MB)

@N:<a href="@N:MF578:@XP_HELP">MF578</a> : <!@TM:1704441242> | Incompatible asynchronous control logic preventing generated clock conversion. 

Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 176MB peak: 177MB)


Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 176MB peak: 177MB)


Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 176MB peak: 177MB)

@N:<a href="@N:FX1184:@XP_HELP">FX1184</a> : <!@TM:1704441242> | Applying syn_allowed_resources blockrams=10 on top level netlist prox_detect  

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 177MB peak: 177MB)



<a name=mapperReport6></a>Clock Summary</a>
******************

          Start                                            Requested     Requested     Clock                                                        Clock                   Clock
Level     Clock                                            Frequency     Period        Type                                                         Group                   Load 
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       prox_detect|clk                                  200.0 MHz     5.000         inferred                                                     Inferred_clkgroup_0     21   
1 .         rpr0521rs_driver|clk_400khz_derived_clock      200.0 MHz     5.000         derived (from prox_detect|clk)                               Inferred_clkgroup_0     180  
2 ..          rpr0521rs_driver|dat_valid_derived_clock     200.0 MHz     5.000         derived (from rpr0521rs_driver|clk_400khz_derived_clock)     Inferred_clkgroup_0     35   
1 .         segment_scan|clk_40khz_derived_clock           200.0 MHz     5.000         derived (from prox_detect|clk)                               Inferred_clkgroup_0     30   
=================================================================================================================================================================================



Clock Load Summary
***********************

                                              Clock     Source                        Clock Pin                Non-clock Pin     Non-clock Pin
Clock                                         Load      Pin                           Seq Example              Seq Example       Comb Example 
----------------------------------------------------------------------------------------------------------------------------------------------
prox_detect|clk                               21        clk(port)                     u4.cnt[8:0].C            -                 -            
rpr0521rs_driver|clk_400khz_derived_clock     180       u1.clk_400khz.Q[0](dffre)     u1.num_delay[23:0].C     -                 -            
rpr0521rs_driver|dat_valid_derived_clock      35        u1.dat_valid.Q[0](dffe)       u2.prox_dat0[15:0].C     -                 -            
segment_scan|clk_40khz_derived_clock          30        u4.clk_40khz.Q[0](dffr)       u4.seg_sck.C             -                 -            
==============================================================================================================================================

<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="e:\fpgaproject\stepbaseboard\step-mxo2 4.0\lab8_prox_detect\source\rpr0521rs_driver.v:49:1:49:7:@W:MT529:@XP_MSG">rpr0521rs_driver.v(49)</a><!@TM:1704441242> | Found inferred clock prox_detect|clk which controls 21 sequential elements including u1.cnt_400khz[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0
For details review file gcc_ICG_report.rpt


@S |Clock Optimization Summary



<a name=clockReport7></a>#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[</a>

1 non-gated/non-generated clock tree(s) driving 21 clock pin(s) of sequential element(s)
3 gated/generated clock tree(s) driving 245 clock pin(s) of sequential element(s)
0 instances converted, 245 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
<a href="@|L:E:\fpgaproject\stepbaseboard\STEP-MXO2 4.0\lab8_prox_detect\impl1\synwork\prox_detect_impl1_prem.srm@|S:clk@|E:u4.clk_40khz@|F:@syn_dgcc_clockid0_2==1@|M:ClockId_0_2 @XP_NAMES_BY_PROP">ClockId_0_2</a>       clk                 port                   21         u4.clk_40khz   
=======================================================================================
================================================================ Gated/Generated Clocks ================================================================
Clock Tree ID     Driving Element        Drive Element Type     Unconverted Fanout     Sample Instance        Explanation                               
--------------------------------------------------------------------------------------------------------------------------------------------------------
<a href="@|L:E:\fpgaproject\stepbaseboard\STEP-MXO2 4.0\lab8_prox_detect\impl1\synwork\prox_detect_impl1_prem.srm@|S:u4.clk_40khz.Q[0]@|E:u4.state[1]@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0 @XP_NAMES_BY_PROP">ClockId_0_0</a>       u4.clk_40khz.Q[0]      dffr                   30                     u4.state[1]            Derived clock on input (not legal for GCC)
<a href="@|L:E:\fpgaproject\stepbaseboard\STEP-MXO2 4.0\lab8_prox_detect\impl1\synwork\prox_detect_impl1_prem.srm@|S:u1.dat_valid.Q[0]@|E:u2.prox_dat2[11:9]@|F:@syn_dgcc_clockid0_3==1@|M:ClockId_0_3 @XP_NAMES_BY_PROP">ClockId_0_3</a>       u1.dat_valid.Q[0]      dffe                   35                     u2.prox_dat2[11:9]     Derived clock on input (not legal for GCC)
<a href="@|L:E:\fpgaproject\stepbaseboard\STEP-MXO2 4.0\lab8_prox_detect\impl1\synwork\prox_detect_impl1_prem.srm@|S:u1.clk_400khz.Q[0]@|E:u1.state[8]@|F:@syn_dgcc_clockid0_5==1@|M:ClockId_0_5 @XP_NAMES_BY_PROP">ClockId_0_5</a>       u1.clk_400khz.Q[0]     dffre                  180                    u1.state[8]            Derived clock on input (not legal for GCC)
========================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N:<a href="@N:FX1143:@XP_HELP">FX1143</a> : <!@TM:1704441242> | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 177MB peak: 177MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 178MB peak: 178MB)


Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 179MB peak: 179MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 97MB peak: 179MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jan  5 15:54:02 2024

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